With development in the semiconductor technologies, all parts in integrated circuits need to be scaled further and are integrated more intensively, thus the number of the conductor wires in circuits is increasing with pitch and width of wires being reduced, which results in more serious parasitic effect between a resistor (R) and a capacitor (C) in conductor wire and causes serious transmission delay (RC Delay). In the advanced process, aforesaid issues become the major factors that limit signal transmission speed in circuits.
Metal Cu instead of Al has been widely used as material for conducting interconnect (or interior metal wiring layer) because of its high melting point, low resistivity and high anti-electron-migration capability, so as to reduce interconnect resistance. Besides, low dielectric constant (low-K) materials have been widely used to reduce parasitic capacitance. In 90 nm technology node process, high density low-k dielectric materials with dielectric constant in the range of 2.8-3.0 have been used to form inter-level dielectric layers, whereas in the process of 65 nm technology or beyond, requirements for porous low-k dielectric materials with a dielectric constant smaller than 2.4 have been proposed to use. These porous low-k dielectric materials, for example, porous MSQ, porous PAE, porous SiLK and porous SiO2, have lower dielectric constants, and are able to further reduce parasitic capacitance and improve circuit speed. However, these materials have such disadvantages as delamination, cohesive cracking and diffusion, as shown in FIGS. 1A and 1B. FIG. 1A illustrates a partially enlarged view of a porous low-k dielectric material, and FIG. 1B illustrates an inter-level dielectric layer 110 made of said porous low-k dielectric material and a wire 120 formed therein. The inherent disadvantages of these materials bring forth significant challenges to the process integration. For example, the porous materials may delaminate or crack in a process involved with mechanical forces, for example, Chemical Mechanical polish (CMP), wafer cutting, wafer packaging or the like. Additionally, since the porous low-k dielectric material contains more than 20% holes, which are distributed irregularly and may also be continuous, the materials used in other processes, for example, a polishing material, a metal material or the like, shall diffuse into these holes, which may give rise to change of the dielectric constant of the dielectric material and shorts between wires 120, and even further impair the stability and reliability of the device.
Therefore, there is a need to propose an inter-level dielectric layer capable of reducing RC delay parasitic capacitance while being easy to integrate, a method for manufacturing the same and a semiconductor device having the inter-level dielectric layer.